Languages for simulation and synthesis

Semestr: Winter

Range: 14+4c

Completion:

Credits: 4

Programme type: Undefined

Study form: Parttime

Course language:

Summary:

The aim of this course is to familiarize the students with simulating digital circuits. General principles and possible strategies for simulation of circuits are mentioned as well, but the main stress is put on teaching the simulation system VHDL. This language is used as the working tool for seminars, labs and for elaborating semester works.

Keywords:

Synchronous and asynchronous simulation, types od delays, entity, architecture, process, sensitivity list, resolution function, data-flow statements, signal attributes, components, configuration.

Course syllabus:

1. Introduction to simulation, basic notions, abstract levels of digital circuit description
2. Domain of simulation values, synchronous and asynchronous simulation, general principles of simulators
3. Introduction to VHDL, entities, architectures, interfaces
4. Review of data types in VHDL
5. Special data types, mathematical libraries, conversions, operations, and resolution functions
6. Sequential environment: processes, sensitivity list, types of sequential statements and types of delays
7. Sequential environment: models of combinatorial and sequential circuits, procedures, functions
8. Automata models, signals and their attributes
9. Sequential environment: shared variables, mutual synchronization of processes
10. Parallel environment: data-flow description, types of parallel statements
11. Parallel environment: models of combinatorial and sequential circuits, testbenches
12. Parallel environment: structural description, component configuration
13. Parallel environment: blocks, guarded blocks, guarded statements, guarded signals, disconnecting drivers
14. Configuration of structural architectures

Seminar syllabus:

1. Introduction to seminars, basic notions
2. Possible strategies for the simulation of structural circuits
3. Familiarizing the VHDL ModelSim environment
4. One-level entity and architecture declaration, generation of simple signals
5. Processes: functional models of combination circuits
6. Processes: using mathematical libraries, resolution functions
7. Processes: functional modeling flip-flops and latches of different types
8. Processes: automata models
9. Demonstrating functional models of complex circuits in sequential environment (ALU, controller, etc.)
10. Models of automata, combination and sequential circuits in parallel environment
11. Designing testbenches
12. Creating structural models of digital circuits
13. Using guarded blocks and guarded signals for creating models
14. Assessment

Literature:

1. Lipsett R., Sheffer C.F., Ussery C: : VHDL: Hardware Description and Design, Kluwer Academic Publishers, London 1989
2. Sjoholm S., Lindh L.: VHDL for Designers, Prentice Hall 1997
3. Dewey A.M.: Analysis and Design of Digital Systems with VHDL, PWS Publishing Company, Boston 1997
4. Ercegovac M.,, Lang T., Moreno H.: Introduction to Digital Systems, John Wiley 1999

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