Architecture of Computer Systems

Semestr: Winter

Range: 2+2s

Completion:

Credits: 5

Programme type: Undefined

Study form:

Course language: English

Summary:

The course deals with architecture of uniprocessor computers on the level of machine instructions with emphasis to instruction pipelining and memory hierarchy. Students are introduced to main topics from RISC and CISC architectures. Second part of the course describes vector processors and shared-memory multiprocessor systems.

Keywords:

computer architecture, processor architecture, instruction pipelining, superscalar processors, memory hierarchy, cache, virtual memory, vector computers, multiprocessor systems, shared memory, coherency and consistency, synchronization, distributed memory.

Course syllabus:

1. Computer performance evaluation, quantitative principles of computer architecture
2. Instruction set architecture, RISC and CISC
3. Introduction to pipelining, integer pipeline of RISC
4. Advanced pipelining, hazard resolving, multicycle instructions
5. Superscalar and superpipelined processors, pipelining of complex instructions
6. Dynamic scheduling and dynamic branch prediction, limits of instruction-level parallelism
7. Memory hierarchy - cache
8. Memory hierarchy - main memory
9. Memory hierarchy - virtual memory
10. Data-level parallelism, vector and SIMD architectures
11. Shared memory multiprocessors, coherency and consistency
12. Processor synchronization in shared memory multiprocessors
13. Multiprocessor systems with distributed memory.
14. Perspectives of further development of computer systems

Seminar syllabus:

1. Computer performance evaluation
2. Measurement of computer performance with benchmark sets
3. Instruction set of DLX, the role of compiler
4. Experiments with integer DLX pipeline
5. Experiments with integer DLX pipeline
6. Simulation of pipelined DLX
7. Simulation of pipelined DLX
8. Evaluation of assignments, reserve
9. Design and simulation of cache
10. Performance simulation of cache
11. Simulation of DLXV
12. Simulation of DLXV
13. Simulation of MESI protocol
14. Assessment

Literature:

1. Hennesy, J. L., Patterson, D. A.: Computer Organization and Design : The Hardware / Software Interface, Third Edition, Morgan Kaufmann Publishers, 2004
2. Hennesy, J. L., Patterson, D. A.: Computer Architecture : A Quantitative Approach, Third Edition, San Francisco, Morgan Kaufmann Publishers, Inc., 2002
3. Dvořák,V.-Drábek,V: Architektura procesorů. Nakl. VUT v Brně, VUTIUM 1999.

Examiners:

Lecturers:

Instructors: