Seminars on Architectures of Parallel Computers

Semestr: Summer

Range: 2+0s

Completion:

Credits: 4

Programme type:

Study form:

Course language:

Summary:

Overview of architectures of high-performance computers and trends in technologies. Memory coherence and sequential consistency models. Shared-memory architectures: buses and switches, bus-based cache coherence protocols and synchronization mechanisms. Virtual shared memory architectures: distributed cache-coherence protocols. Synchronization mechanisms - barriers. Clusters: fast communication networks and protocols.

Keywords:

Course syllabus:

1. Memory coherence and consistency models.
2. Shared memory architectures: fast busses and switches.
3. Shared memory architectures: coherence snooping algorithms.
4. Shared memory architectures: synchronization mechanisms.
6.-8. Virtual Shared memory architectures: cache coherence protocols.
9.-11. Distributed memory architectures: synchronization mechanisms and algorithms.
12.-14. Workstation clusters: fast interconnects and network protocols.

Seminar syllabus:

Literature:

D.E.Culler, et al. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann Publ., 1999, ISBN 1-55860-343-3.

Examiners:

Lecturers:

Instructors: