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ING. MILOŠ BEČVÁŘ

Buryan, P. 2014 Refinement Action-Based Framework for Utilization of Softcomputing in Inductive Learning, detail

Kubátová, H., Bečvář, M., Novotný, M. 2012 Softwarové jádro procesoru ADOP, detail

Zemanová, M. 2012 Exploiting Ontologies and Higher Order Knowledge in Relational Data Mining, detail

Karel, F. 2009 Quantitative Association Rules Mining, detail

Bečvář, M., Kahánek, S. 2007 VLIW-DLX simulator for educational purposes, detail

Šimek, M., Brabec, T., Bečvář, M. 2006 Running Linux on an FPGA-based Embedded Platform, detail

Bečvář, M., Kubátová, H., Novotný, M. 2006 Massive Digital Design Education for Large Amount of Undergraduate Students, detail

Bečvář, M., Štukjunger, P. 2005 Fixed-Point Arithmetic in FPGA, detail

Bečvář, M., Brabec, T. 2005 Algorithm Acceleration in Programmable System on Chip, detail

Bečvář, M., Štukjunger, P. 2005 Fixed-Point Arithmetic in FPGA, detail

Brabec, T., Bečvář, M. 2004 Modern Tools for Reconfigurable SoC Design, detail

Bečvář, M., Brabec, T. 2004 Implementation of Configurable System on a Chip With Microblaze Processor Core, detail

Bečvář, M., Štukjunger, P. 2004 Implementation of Basic Arithmetic Operations in FPGA, detail

Bečvář, M. 2004 Teaching Basics of Instruction Pipelining with HDLDLX, detail

Bečvář, M. 2003 Optimization of Simple CPU Core for FPGA, detail

Bečvář, M., Pluháček, A., Daněček, J. 2003 DOP - a CPU Core for Teaching Basics of Computer Architecture, detail

Bečvář, M., Pluháček, A., Daněček, J. 2003 DOP - A Simple Processor Core for Educational Purposes, detail

Jáchim, M., Jäger, M., Bečvář, M. 2002 Tuning up the PCI Devices, detail

Schmidt, J., Novotný, M., Jäger, M., Bečvář, M., Jáchim, M. 2002 Exploration of Design Space in ECDSA, detail

Kubátová, H., Bečvář, M. 2002 FEL-Code: FSM Internal State Encoding Method, detail

Bečvář, M., Jäger, M., Jáchim, M. 2002 FPGA Implementation of CRC, detail

Schmidt, J., Novotný, M., Jäger, M., Bečvář, M., Jáchim, M. 2002 Comparison of the Polynomial and Optimal Normal Basis ECDSA for GF(2^162), detail

Jáchim, M., Jäger, M., Bečvář, M. 2002 Elliptic Coprocessor GF(2^162], detail

Pluháček, A., Douša, J., Daněček, J., Bečvář, M. 2001 Návrh procesorů ve výuce, detail

Bečvář, M., Schmidt, J. 2001 Reconfigurable Acceleration of Intel PC: A Quantitative Analysis, detail

Bečvář, M., Daněk, M., ElShafey, K., Hlavička, J., Schmidt, J. 2001 Architecture Acceleration using FPGAs, detail

Bečvář, M., Jáchim, M., Jäger, M. 2001 Case Study: FPGA Acceleration of CRC Computation, detail

Bečvář, M. 2000 Advantage of using FPGA for Implemntation of Interfaces in the VoN Applications, detail

Jiřina, M. 1998 Initial Setting of Weights in the Kohonen Maps, detail

Rozinek, J. 1996 Predikce časových řad neuronovými sítěmi, detail