A Set of Logic Design Benchmarks

Fišer, P., Hlavička, J.

FIŠER, P. and J. HLAVIČKA. A Set of Logic Design Benchmarks. In: STRAUBE, B., et al., eds. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002. Design and Diagnostics of Electronic Circuits and Systems, Brno, 2002-04-17/2002-04-19. Brno: VUT v Brně, 2002. p. 324-327. ISBN 80-214-2094-4.